A pad driver circuit may be a part of an integrated circuit which interfaces a chip core (e.g., IC core) with an external world. The pad driver circuit may have to drive a load which has a capacitive range under a slew rate control condition. A slew rate may be a maximum rate of change of a signal at any point in a circuit. Under the slew rate control condition (e.g., where the pad driver circuit needs to drive a wider capacitive load), the pad driver may need a pad feedback (e.g., Miller feedback) to control the slew rate.
However, the deployment of the pad feedback may force conduction of an NMOS component in the pad driver circuit. Conduction of the NMOS component may not be favorable since conduction of the NMOS component at a fail safe state of the integrated circuit may cause current to be drawn from a pad node which in turn causes a drop of voltage at a communication line where the pad driver is connected. This drop in voltage at the communication line may hamper communication and/or input to an other device (e.g., an other IC, etc.) that is connected to the communication line.